Field isolation regions are used in integrated circuit memory arrays to isolate memory cells from each other. EPROMS (erasable and programmable memories) are a type of CMOS transistor array that requires field isolation. Most EPROMs being manufactured today have single-transistor memory cells. The transistor has a double-poly gate structure, or "stack" in which an upper poly forms the control gate and wordlines and a lower poly forms a floating gate. Field oxide (FOX) regions are used to provide desired capacitive coupling between these gates, as well as to isolate adjacent cells.
FIG. 1A illustrates the FOX regions of a portion of a conventional single-transistor memory cell array. A particular example of such an array is an EEPROM (electrically erasable and programmable memory). In conventional fabrication, a "moat mask" defines the active areas, including source lines that run parallel to rows of cells and connect transistor source regions. The FOX regions are grown by a localized field oxidation (LOCOS) process in areas not protected by the moat mask. They form a pattern of "islands", each designed to have a sideways "H" shape. Cells having this pattern of FOX regions are sometimes referred to as "H cells". They are also sometimes referred to as "T cells" because the active areas are T-shaped.
Despite the straight-edged design of the FOX regions, after fabrication, their actual shape resembles a "dog bone", as illustrated by the dotted lines The FOX regions are rounded instead of square. This rounding occurs as a result of limitations of photolithography optical resolution and a different oxidation rate at corner areas.
Cell designs for other types of CMOS memory devices have similar problems with rounded field oxide region corners. FIG. 1B illustrates another such design, commonly known as the "X cell" design because its moat areas have the pattern of crossed lines throughout the array. Transistor gates are connected as wordlines. The dotted lines indicate the corner rounding that occurs when these arrays are fabricated by conventional techniques.
The rounded ends of the FOX regions have undesirable effects, well known in the art of semiconductor fabrication. For example, in FIG. 1A, if misalignment occurs between the field oxide regions and transistor gates, the channel widths of two adjacent transistors across the source line may differ, and the channel widths may vary across the length of each transistor. If cells in two adjacent rows share a source line, as is the case in some memory array layouts such as flash EEPROMs having a "double poly" structure, the capacitive coupling ratio between the control gate and floating gate may vary from cell to cell across the source line. The result is unequal programming and erase characteristics, leading to bimodality distributions. The same problems would manifest in an X-cell array, only in this case, the problem would be quadmodal distributions in program and erase characteristics. An additional problem is that gate oxide near the interface of LOCOS/channel oxide is generally inferior to the channel oxide away from this interface. This is the result of oxide/nitride layers used to relieve stress during LOCOS.
An alternative to LOCOS methods for forming field oxidation regions is to initially form a thick oxide layer. Moats are then directly etched in this layer to form alternating columns of moats and field oxide regions. This process is known as a "direct moat etch." However, a problem with direct moat etching is that if the sidewalls are steep, the completed structure may contain poly filaments that lead to reliability problems.
A need exists for a structure and method of fabricating isolation regions for CMOS memory arrays that avoids (1) a LOCOS/channel interface, (2) field oxide regions with rounded corners, and (3) the problems of direct moat etching.